1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor.
2. Description of Related Art
As the level of integration in integrated circuits continues to increase, area occupation of each semiconductor device is reduced. Consequently, the specification in circuit design must be changed to reflect such reduction. At present, integrated circuits are designed to have feature dimensions in the deep sub-micron range. However, as the integrated circuit device such as a deep sub-micron metal-oxide-semiconductor (MOS) device is miniaturized, depth of the source/drain terminal within a substrate must be reduced in a corresponding way. Yet, the reduction of the junction depth of the source/drain terminal must not result in any increase in resistance. In fact, the capacity to produce a source/drain terminal with all the desired specifications is a major factor that determines the ultimate quality of a MOS transistor.
The conventional method of fabricating a MOS transistor involves the following steps. First, a pre-amorphization implantation is carried out on a substrate having a gate structure thereon. Thereafter, an extension region and doped source/drain region are sequentially formed in the substrate. A rapid thermal annealing operation is carried out to initiate a re-crystallization of silicon in the amorphized region and activate the dopants within the extension region and the doped source/drain region to form a source/drain terminal. The annealing operation is carried out a high temperature of between 800° C. to 900° C. Although the pre-amorphization implantation is able to lower the channel effect due to the dopants, the diffusion of dopants cannot be prevented.
Another conventional method of fabricating a MOS transistor involves the following steps. First, an amorphization implantation using germanium ions is carried out on a substrate with a gate structure thereon. Thereafter, an extension region and doped source/drain region are sequentially formed within the amorphized region of the substrate. A solid phase epitaxial fabrication process is carried out to re-crystallize the silicon in the amorphized region and activate the dopants within the extension region and the doped source/drain region to form a source/drain terminal. However, the resistance at the source/drain terminal is still relatively high and the saturated drain current is still relatively low for a MOS transistor fabricated using this method.